1. Field of the Invention
The present invention generally relates to electronic systems which transmit signals to remote devices via signal lines, and more particularly to an electronic system which transmits a signal having an amplitude less than the power supply voltage applied to the electronic system. Further, the present invention is concerned with a semiconductor integrated circuit and a termination device used in such an electronic system.
2. Description of the Prior Art
Recently, there has been considerable activity in the development of small-amplitude high-speed signal transmissions. In such transmissions, signals having amplitudes less than the power supply voltage are transmitted. For example, the GTL (Gunning Transceiver Logic) standard is known. According to this GTL standard, the output circuit is an open-drain type driver and an impedance match termination is employed. Under these conditions, the following parameters are defined:
termination voltage V.sub.TT =1.2 V .+-.5%; PA1 reference voltage V.sub.REF =0.8 V; PA1 output high-level voltage V.sub.OH 0.8 V+400 mV; PA1 output low-level voltage V.sub.OL =0.8 V-400 mV; PA1 input high-level voltage V.sub.IN =0.8 V+50 mV; and PA1 input low-level voltage V.sub.IN =0.8 V-50 mV.
Regarding the small-amplitude high-speed signal transmissions, the following documents are known: 1) Taguchi et al., "COMPARING SMALL-AMPLITUDE INTERFACES TOWARD 100 MHZ TIMES", Nikkei Electronics, No. 591, pp. 269-290, 1993. 9. 27; and 2) Taguchi et al., "SMALL-AMPLITUDE INTERFACE CIRCUIT FOR HIGH-SPEED MEMORY BUS", Study Document of Institute of Electronics, Communication and Information Engineers, Nov. 26, 1993.
FIG. 1 is a block diagram of a system having electronic systems in which a small-amplitude signal, which has an amplitude less than the power supply voltage, is transmitted therebetween via a bus line. The system shown in FIG. 1 includes a microprocessor 1, SDRAM (Synchronous Dynamic Random Access Memory) devices 2.sub.1, 2.sub.2 and 2.sub.n (where n is an integer), and a bus line 3 via which small-amplitude signals are transmitted. At the present time, the transmission of signals between the microprocessor 1 and the DRAM devices 2.sub.1 -2.sub.n are carried out at tens of mega-hertz. However, it is required that signal transmissions be performed at 100 MHz or higher.
FIG. 2 is a circuit diagram of conventional interfaces and a bus system employed in electronic systems as described above. A microprocessor 5 has a signal input/output terminal 6, a reference voltage input terminal 7 and an input circuit 8. The signal input/output terminal 6 is used to input and output a signal DQ. The reference voltage input terminal 7 is used to receive a reference voltage Vref. The input circuit 8 includes a differential amplifier circuit. Further, the microprocessor 5 has a VCC power supply line 10 providing a power supply voltage VCC (equal to, for example, 3.3 V), a VSS power supply line via which a power supply voltage VSS (equal to, for example, 0 V), a main body circuit 11 and a push-pull-type output circuit 12.
The push-pull-type output circuit 12 is made up of an enhancement-type p-channel MOS transistor 13 functioning as a pull-up element, and an enhancement-type n-channel MOS transistor 14 functioning as a pull-down element.
A bus line 15 transmits small-amplitude signals. A termination voltage supply 16 generates a termination voltage VTT (equal to, for example, 1.65 V). A VTT voltage line 17 supplies the termination voltage VTT to parts connected thereto. Two termination resistors 18 and 19 (equal to, for example, 50.OMEGA.) are connected as shown in FIG. 2. An SDRAM device 20 has a signal input/output terminal 21 used to input and output the signal DQ, a reference voltage input terminal 22 receiving the reference voltage Vref, an input circuit 23 having a differential amplifier circuit, and a push-pull-type output circuit 24.
In the configuration shown in FIG. 2, the termination voltage VTT generated from the termination voltage supply 16 is applied, as the reference voltage Vref, to the reference voltage input terminal 7 of the microprocessor 5 and the reference voltage input terminal 22 of the SDRAM 20.
In the interface circuits and the bus system shown in FIG. 2, the signal DQ is transmitted in such a way that a center voltage is set equal to the reference voltage Vref (=1.65 V), and the amplitude is within the range of .+-.400 mV. For example, when the microprocessor 5 sends the signal DQ to the DRAM device 20, the pMOS transistor 13 is turned OFF (not conducting), and the nMOS transistor 14 is turned ON (conducting). In this case, the signal DQ is set to the low level (L). When the pMOS transistor 13 is turned ON and the nMOS transistor 14 is OFF, the signal DQ is switched to the high level (H). When the output circuit 12 outputs the low level, a current flows from the termination voltage supply 16 to the load. When the output circuit 12 outputs the high level, a current flows the termination voltage supply 16 from the load.
Generally, the termination voltage supply 16 is formed with a voltage source such as a switching regulator or a series regulator. However, such a regulator is not expected to receive current coming from the power supply. If a current comes into the voltage source from the load, the termination voltage VTT will be varied.
Taking into account the above, a bus system as shown in FIG. 3 can be used. The bus system shown in FIG. 3 includes a power supply voltage generating circuit 25 for generating the power supply voltage VCC. The circuit 25 is connected to a VCC power supply line 26. Further, there is provided a VSS power supply line 27. Further, the system includes termination resistors 28-31 (each equal to, for example, 100.OMEGA.), voltage dividing resistors 32 and 33, and power supply voltage input terminals 34 and 35 of the microprocessor 5. The resistors 32 and 33 divide the power supply voltage VCC to thereby generate the reference voltage Vref.
In the bus system, the termination part made up of the termination resistors 28 and 29 is set approximately equal to 50.OMEGA., and the termination part made up of the termination resistors 30 and 31 is set approximately equal to 50.OMEGA..
However, the bus system shown in FIG. 3 has the following disadvantages. The termination resistors 28 and 29 as well as the termination resistors 30 and 31 are respectively connected in series between the VCC line 26 and the VSS line 27. Hence, even when no signal is transmitted, currents flow in the termination resistors 28-31 and increase power consumption.
If the voltage dividing resistors 32 and 33 are designed to have large resistance values, the current flowing in the resistors 32 and 33 can be reduced. However, if the resistors 32 and 33 do not have good precision, the reference voltage Vref will not be equal to the termination voltage VTT. The difference between the reference voltage Vref and the termination voltage VTT functions as a D.C. offset voltage of the input signal, which reduces the operation margin at the high-level or low-level side of the input signal. Hence, it is necessary to use high-precision resistors 32 and 33. However, this leads to an increase in the production cost.